High-Level Test Synthesis of Digital VLSI Circuits

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Here is the first book to propose HTS as a complete, more effective VLSI circuit design approach. It explains how HTS is able to explore the synthesis freedom provided at high level to derive an inherently testable architecture at low or even no overhead. The book provides an introduction to HTS and helps you develop a comprehensive understanding of this emerging technology by presenting a complete background of HTS terms, operation scheduling, and resource allocation algorithms. It also covers various HTS techniques for scan and built-in self-test methodologies, register-transfer level test synthesis, examples of several effective HTS schemes for highly testable digital circuits, and more.